1. Field of the Invention
The present invention relates to the preparation of semiconductor substrates and to semiconductor circuits incorporating MOS devices, such as static random access memories (SRAMs).
2. Description of the Related Art
A variety of semiconductor circuits incorporate MOS devices formed within isolation wells. Of particular note are the semiconductor circuits which include NMOS devices, such as SRAMs of the type which incorporate NMOS and PMOS field effect transistors within memory and input/output (I/O) circuits. Conventionally, the NMOS devices of such an SRAM are formed within P-type isolation wells to improve the performance of the NMOS devices, regardless of whether the NMOS devices are part of the SRAM memory cells or whether the NMOS devices are within the I/O circuitry of the SRAM. Typically, P-type isolation wells are formed within N-type regions. For example, SRAMs may be formed in N-type silicon substrates so that a p/n junction is formed at the boundary between the N-type substrate and the P-type wells in which the NMOS devices of the SRAM are formed. The p/n junction formed between the P-type well and N-type substrate limits the loss of data from memory cells caused by either I/O bounce or alpha-particle decay by isolating the active regions of the memory cell devices from the substrate in which noise carriers are generated. I/O bounce can inject free charge carriers into the substrate of a semiconductor device in response to the presence of noise signals on the input or output terminals of the device. Alpha-particle decay within the substrate also generates free carriers in the substrate. If the NMOS devices of a semiconductor circuit were not formed within isolation wells, then carriers injected into the substrate or generated within the substrate could reach the active region of the NMOS device, resulting in the loss of data. When NMOS devices are formed within P-type isolation wells having a p/n junction separating the isolation well from the N-type substrate, carriers injected into the substrate or generated within the substrate generally do not reach the active region of the NMOS device because of the potential barrier associated with the p/n junction between the P-type well and the N-type substrate.
While N-type silicon substrates provide desirable performance advantages for NMOS devices which incorporate P-type isolation wells, the use of N-type substrates has two significant disadvantages when compared to the use of P-type silicon substrates. First, N-type silicon substrates are more expensive than P-type silicon substrates. It would be desirable to use P-type silicon substrates to reduce the cost of producing semiconductor circuits which include NMOS devices formed within P-wells. Second, microprocessors and other types of logic circuits are typically formed on P-type substrates. It would be desirable to develop a process whereby MOS devices which utilize P-type isolation wells could be formed on the same substrate with microprocessors or logic circuits, providing better system integration and allowing the formation of more complex semiconductor circuit.